1. Field of the Invention
The present invention relates to a semiconductor device, more particularly, to a dynamic random access memory (DRAM) comprising memory cells, each of which is composed of a transistor and a capacitor.
2. Description of the Related Art
System expansion and developments in technology have brought about an ongoing increase in the storage capacity of the DRAM, and have given rise to a requirement for reducing the size of a memory cell. In order to secure a sufficient charge in a small cell area, a trench-capacitor formed in a groove dug in a semiconductor substrate has been proposed and used as a capacitor for the charge storage of information.
Taking into consideration the demand for a high speed operation of the memory device, a silicon on insulator (SOI) structure has been proposed and adopted in the memory device which prevents an increase of the signal delay time caused by a parasitic capacitance, and decreases a memory cell area.
There are also demands for a method of increasing a capacitance of a capacitor by making a dielectric layer thin, in the device using the above-mentioned two structures, and conversely, for a method of improving the reliability of the dielectric layer by decreasing the electric field strength applied to the capacitor when a dielectric layer has the same thickness as that of the thinned dielectric layer. A DRAM device was proposed by the present inventor in EP-A-No. 0145606 (European Patent Application No. 84402560.1 filed on Dec. 12, 1984). For example, one of the memory cells comprises a field effect transistor (FET) and a trench-capacitor, as shown in FIG. 9 of EP-A-No. 0145606 (corresponding to U.S. Ser. No. 681,290). In the drawing, the FET has a source region and a drain region which are formed in a semiconductor substrate, and the capacitor comprises a dielectric (insulation) layer formed on the groove surface, an upper capacitor electrode (conductive layer) formed on the dielectric layer and connecting with the drain region, and a lower capacitor electrode which is a diffusion region formed in the substrate and along the groove surface. In this case, the SOI structure is not adopted in the memory device, so that the parasitic capacitance affects the memory device. Furthermore, the restrictions of integration prevent an electrode connecting with the diffusion region of the lower capacitor electrode from forming, so that a low level voltage cannot be applied to the lower capacitor electrode. Accordingly, the capacitor is supplied with a supply voltage V.sub.CC or a total voltage of V.sub.CC and a substrate bias voltage. When the capacitor using a thin dielectric (insulation) layer is supplied with such a voltage, degradation of the reliability of the thin dielectric layer becomes a problem, and as a result, the reliability of the memory device is degraded.